Viewing file: fp16fml_lane_low.c (1.98 KB) -rw-r--r-- Select action/file-type: (+) | (+) | (+) | Code (+) | Session (+) | (+) | SDB (+) | (+) | (+) | (+) | (+) | (+) |
/* { dg-do compile } */ /* { dg-require-effective-target arm_fp16fml_neon_ok } */ /* { dg-add-options arm_fp16fml_neon } */
#include "arm_neon.h"
float32x2_t test_vfmlal_lane_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b) { return vfmlal_lane_low_f16 (r, a, b, 0); }
float32x2_t test_vfmlsl_lane_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b) { return vfmlsl_lane_low_f16 (r, a, b, 0); }
float32x2_t test_vfmlal_laneq_low_f16 (float32x2_t r, float16x4_t a, float16x8_t b) { return vfmlal_laneq_low_f16 (r, a, b, 6); }
float32x2_t test_vfmlsl_laneq_low_f16 (float32x2_t r, float16x4_t a, float16x8_t b) { return vfmlsl_laneq_low_f16 (r, a, b, 6); }
float32x4_t test_vfmlalq_lane_low_f16 (float32x4_t r, float16x8_t a, float16x4_t b) { return vfmlalq_lane_low_f16 (r, a, b, 1); }
float32x4_t test_vfmlslq_lane_low_f16 (float32x4_t r, float16x8_t a, float16x4_t b) { return vfmlslq_lane_low_f16 (r, a, b, 1); }
float32x4_t test_vfmlalq_laneq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b) { return vfmlalq_laneq_low_f16 (r, a, b, 7); }
float32x4_t test_vfmlslq_laneq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b) { return vfmlslq_laneq_low_f16 (r, a, b, 7); }
/* { dg-final { scan-assembler-times {vfmal.f16\td[0-9]+, s[123]?[02468], s[123]?[02468]\[0\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmal.f16\td[0-9]+, s[123]?[02468], s[123]?[13579]\[0\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmal.f16\tq[0-9]+, d[123]?[02468], d[0-9]+\[1\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmal.f16\tq[0-9]+, d[123]?[02468], d[123]?[13579]\[3\]} 1 } } */
/* { dg-final { scan-assembler-times {vfmsl.f16\td[0-9]+, s[123]?[02468], s[123]?[02468]\[0\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmsl.f16\td[0-9]+, s[123]?[02468], s[123]?[13579]\[0\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmsl.f16\tq[0-9]+, d[123]?[02468], d[0-9]+\[1\]} 1 } } */ /* { dg-final { scan-assembler-times {vfmsl.f16\tq[0-9]+, d[123]?[02468], d[123]?[13579]\[3\]} 1 } } */
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